Verification Techniques for System-Level Design Hardback
by Masahiro (Professor, VLSI Design & Education Center, University of Tokyo, Japan.) Fujita, Indradeep (Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.) Ghosh, Mukul (Senior Researcher, Fujitsu Labs of America, Sunnyvale, CA, USA.) Prasad
Part of the Systems on Silicon series
Hardback
- Information
Description
This book will explain how to verify SoC (Systems on Chip) logic designs using "formal" and "semiformal" verification techniques.
The critical issue to be addressed is whether the functionality of the design is the one that the designers intended.
Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation.
Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity. For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates.
This book covers all aspects of high-level formal and semiformal verification techniques for system level designs.
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Out of Stockmore expected soon
- Format:Hardback
- Pages:256 pages, Approx. 130 illustrations; Illustrations, unspecified
- Publisher:Elsevier Science & Technology
- Publication Date:12/12/2007
- Category:
- ISBN:9780123706164
