ASIC and FPGA Verification : A Guide to Component Modeling Paperback / softback
Part of the Systems on Silicon series
Paperback / softback
- Other Formats
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components.
Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs.
ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system.
It is a valuable resource for any designer who simulates multi-chip digital designs.