Through-Silicon Vias for 3D Integration Hardback

Publisher's Note: Products purchased from Third Party sellers are not guaranteed by the publisher for quality, authenticity, or access to any online entitlements included with the product. A comprehensive guide to TSV and other enabling technologies for 3D integrationWritten by an expert with more than 30 years of experience in the electronics industry, Through-Silicon Vias for 3D Integration provides cutting-edgeinformation on TSV, wafer thinning, thin-wafer handling, microbumping and assembly, and thermal management technologies.

Applications to highperformance, high-density, low-power-consumption, wide-bandwidth, and small-form-factor electronic products are discussed. This book offers a timely summary of progress in all aspects of this fascinating field for professionals active in 3D integration research and development, those who wish to master 3D integration problem-solving methods, and anyone in need of a low-power, wide-bandwidth design and high-yield manufacturing process for interconnect systems. Coverage includes:Nanotechnology and 3D integration for the semiconductor industryTSV etching, dielectric-, barrier-, and seed-layer deposition, Cu plating, CMP, and Cu revealingTSVs: mechanical, thermal, and electrical behaviorsThin-wafer strength measurementWafer thinning and thin-wafer handlingMicrobumping, assembly, and reliabilityMicrobump electromigrationTransient liquid-phase bonding: C2C, C2W, and W2W2.5D IC integration with interposers3D IC integration with interposersThermal management of 3D IC integration3D IC packaging